In high-performance computing systems, a plurality of independent servers, processor nodes, or processor units provide a distributed architecture that is capable of parallel computing operations. Such distributed computing requires that the servers, processor nodes, or processor units communicate with one another. These independent computing nodes of a high-performance computing system may be connected to one another through a switch. In IBM® pSeries® computing systems, a server, processor node, or processor unit may be connected to a switch through a communications adapter via an input/output (I/O) port of the server, processor node, or processor unit. (The marks IBM and pSeries are registered trademarks of International Business Machines Corporation, Armonk, N.Y.) Each server or processor node may include a plurality of central processing units working together and sharing cache memory.
As processor clock speeds have increased and the data communications rate between the communications adapters and switches have increased, the I/O bus has become a bottleneck that hinders improved performance in such high performance computing systems. Increasing the speed of a processor unit's I/O bus by simply increasing the width and signaling rate of the bus has the disadvantages of being expensive and complex because of physical factors such as the following: the length of the bus, the number of devices that can be fabricated on a chip, chip pin-count limitations, power consumption considerations, and the speed of available error correction systems. For example, one known I/O bus solution simply increases the bus width and provides separate, dedicated buses for address and data transmission. In this solution, the I/O bus' control information takes a different path from the data payload. Although this I/O bus solution increases bandwidth, the cost of implementation is high, and the utilization of the bus system as a whole is relatively very low. Therefore, there is a need for an I/O bus that provides an increased data throughput rate.
There is also a need for an I/O bus to support a wide range of I/O devices, I/O bridges to the standard PCI bus, and other high-speed adapters like IBM® pSeries® High-Performance-Switch-based adapters and Infiniband-based adapters. These I/O components have a wide spectrum of latency and bandwidth requirements. This can lead to conflicting performance requirements. For example, a communications adapter generally requires a fast response time when it issues a Direct Memory Address (DMA) request to a memory component so that the adapter can determine when to reuse a sequence number in a tag field that keeps a record of outstanding DMA requests. On the other hand, to sustain high DMA transfer rate, it is very desirable to maximize the request issue rate. Using existing I/O buses, the number of DMA requests that are retried by the I/O controller increases with an increase in the rate at which the adapter is issuing the DMA requests. As a result, the increase in the number of retries causes an increase the response time and a decrease in the throughput of the bus. Therefore, there is also a need for an I/O bus that provides an increased data throughput rate and reduced latency.